Current mode logic (CML) transmitters are often used in power managed applications. In order to conserve power it is sometimes necessary to turn off the outputs of a CML transmitter. The outputs of a CML transmitter output circuit are turned off by logically driving low the differential CML output gates. When the outputs of the CML transmitter output circuit are switched off, the drain of the bias transistor of the CML transmitter output circuit pulls low.
Then, when the CML transmitter output circuit is subsequently turned back on, the differential outputs of the CML transmitter output circuit are enabled. This causes the drain of the bias transistor of the CML transmitter output circuit to be rapidly pulled up. The Miller coupling capacitance from the drain to the gate of the bias transistor of the CML transmitter output circuit causes the bias voltage to increase. This increase in turn causes the output levels of the CML transmitter output circuit to be too large (i.e., having values that are out of specification) for a period of time that is longer than the time allowed for an “idle to active” transition.
That is, the active state transition (from “idle to active”) disturbs the reference bias circuit voltage in a manner that causes the reference bias circuit voltage to take too long (e.g., one hundred fifty nanoseconds (150 nsec)) to settle down to its steady state value.
Therefore, there is a need in the art for a system and method for providing a bias circuit that permits a fast transition from an idle state (i.e., power down state) to an active state (i.e., power up state) in current mode logic (CML) transmitter output circuits.